The present invention generally relates to hardware development and design, and in particular it relates to a method for simulating hardware.
Although the present invention has a very general scope which is independent of a specific hardware simulation method, it will be compared with a specific prior art, i.e. the hardware simulation of clocked designs in which so-called cycle simulation is used for performance reasons.
In such prior art hardware simulation methods, said cycle simulation implies that the logical behavior of the hardware will be compiled to an executable program that is computed once for every simulation cycle. In general, the performance for such a prior art simulator program is linear to the size of the design. When, for instance the design is duplicated in size an executable object results which is double as large as before and has thus only the half of the former performance. In cycle simulation programs, each Boolean expression of the hardware logic under development has to be compiled into code. This is generally done by looking for each individual bit and translating its Boolean expression into code.
Due to the fact that state-of-the-art computer processors can handle words (32 bit) or even double words (64 bit) at a time, the resulting code which is only using 1 bit per operation for the actual simulation work and which does not exploit for example the remaining 31 or 63 bit for simulation work, is very far from optimum.
In prior art hardware simulation systems, one and the same hardware model is simulated under a plurality of operation conditions which differ from each other by different stimuli. A stimulus is hereby meant to be understood as a general boundary condition of the underlying hardware model. Thus, it can be a different input vector, and often some variation in the initial setup of internal register or array occupancy.
Those models which are identical but differ in a plurality of input variables, are denoted further herein as different instantiations of the same hardware model.
A prior art approach intends to optimize cycle simulation by setting up so-called ‘parallel instance features’. If the hardware design contains some identical pieces it is possible to use the code for one piece and reuse the remaining 31 bits as slices for up to 31 copies of the same original piece of hardware logic. If ever such a situation is present on the chip, this reduces the size of the executable file and therefore increases the performance of the simulation program. Unfortunately, this prior art approach is only efficient if multiple instances of the same piece of hardware are found in one design.
Said prior art approach to use multiple instances for simulation has at least two essential disadvantages. First, it works only in cases when multiple design copies are available in a given hardware circuit design. If this should not be the case—as it is very often—there are no possibilities to make the simulation faster. Second, whenever said ‘multiple instances’ approach is used for reusing code for a plurality of hardware pieces some extra, i.e. separate glue code, is required to connect said multiple instances properly to the rest of the hardware model. This, however represents quite a lot of work and results in considerable computing time consumption.